SI-FPGAIP-SDRAM: Overview
Sheldon Instruments offers a memory controller IP that interfaces to standard SDRAM technology, with a flexible user interface to the memory controller itself.

Key Features

• Programmable CAS latency.
• Burst termination.
• Bank management to minimize ACTIVE commands.
• Supports all standard SDRAM commands.
• Data mask signals for byte lane control.
• Supports multiple data path widths (8, 16, 32, 64, 72).
• Programmable timing parameters.
• Optional SPD interface and parameter configuration for DIMMs.
• Multiple DIMM support including SDRAM, DDR1, DDR2, and DDR3.
• Flexible user interface options to memory controller address.
• Highly integrated into the PCI Express architectures.

User Interface
Two options are available for the user interface to the memory controller address bus:

• a higher level interface using a linear address bus with control lines and data bus, similar to an SRAM interface which allows for quick integration into projects but may increase access latency.
• a lower level interface to more tightly control access, such as read and write counts, which can speed up transfer accesses to the SDRAM if certain information, such as transfer size is known in advance by the interface.

FPGA IP