PCI Express
PCI Express Bus
The PCI Express (PCIe) cores handle all details of PCIe layer implementation with user access to the entire Transaction Layer Packet (TLP), with options for a parallel bus interface on the user side to manage TLP details and configure DMA channels.

SI-FPGAIP-PCIe: Overview
Sheldon Instruments offers a pair of PCIExpress (PCIe) cores with a highly efficient design architecture characterized by low resource utilization and low transmit and receive latencies.

For more demanding applications, Sheldon Instruments can custom design the interface to fit your needs, or provide technical support for those designing their own interfaces.

Key Features

  • 32 bit wide datapath, single lane (x1) interface (64 bit and x4 in development).
  • Highly integrated into the SDRAM Memory Controller architectures.
  • Choice between Pro (complete drop in solution) or Standard cores (for advanced users).
  • Support for Root Complex and Endpoint devices.
  • Integrated DMA and Scatter Gather.
  • Software development kit that includes projects and related source code for Windows and Linux 32/64 bit applications and kernel mode device drivers.

Standard PCIe Core
The Standard PCIe core handles all of the PCIe layer implementation details, starting with the Physical Layer interface, the Data Link Layer, and finishing with user access to the entire Transaction Layer Packet (TLP), which be can extremely advantageous in certain applications which require optimized real-time communications, or a user defined processing layer.

Pro PCIe Core
The Pro PCIe core is a superset of the Standard PCIe core, targeted for general applications with an added Processing Layer that consists of a parallel bus interface to manage TLP details and configure DMA channels, with the convenience of Scatter Gather.

The Pro PCIe core interface is similar to using a PCI to local bus bridge chip such as the PLX 90xx or AMCC 593x. When migrating an existing design from PCI to PCI Express, often times only the smallest device within an FPGA family with an integrated SERDES will suffice.

The FPGA design, interface, and implementation are all simplified with the Pro PCIe core. For example, there are no input or output pin timing constraint requirements, no board level routing requirements, no additional power supplies, and one less device to procure and solder onto the board.

FPGA IP
[table class=”siTB”]
Product, Description, Price (US dollars)
SI-FPGAIP-PCIE, Standard PCIe Core, Call
SI-FPGAIP-PCIE-PRO, Pro PCIe Core, Call
[/table]