SI-FPGAIP-SRIO: Overview
Sheldon Instruments offers a Serial RapidIO (SRIO) core with a highly efficient design architecture characterized by low resource utilization and low transmit and receive latencies, thereby allowing for a simplified point to point topology with minimal protocol complexity that renders extremely high throughput. The SRIO core will be offered exclusively with all of the new SI-DSP carrier cards based on TI’s new line of multicore Keystone devices such as the C66xx and 66AK2Hxx devices. A “generic” parallel expansion port mimicking a standard memory interface will also be available for those who prefer to incorporate their own custom hardware or update legacy designs with minimal effort.

The SRIO core handles all of the layer implementation details, starting with the Physical Layer, the Transport (routing) Layer, and the Logic Layers that supports multiple protocols that define the type of data exchanges between endpoint devices.

For more demanding applications, Sheldon Instruments can custom design the interface to fit your needs, or provide technical support for those designing their own interfaces to the new line of SI-DSP carrier cards.

Key Features

• 32 bit wide datapath, single lane (x1) interface.
• Highly integrated into the SDRAM Memory Controller architectures.
• Seemless handling of all layer implementation details.
• Integrated DMA.
• Transparent layer that translates SRIO to a legacy parallel bus on SI’s new line of C66xx/66AK2Hxx Keystone DSP carrier cards.

FPGA IP
[table class=”siTB”]
Product, Description, Price (US dollars)
SI-FPGAIP-SRIO, SRIO Core, Call
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