The SI-C6713DSP from Sheldon Instruments is a family of powerful Digital Signal Processor (DSP) cards for your PC equipped with a 32 bit PCI bus. It is based on Texas Instruments’ 300Mhz TMS320C6713, 32 bit DSP, and can transform your system into an ultra high performance development platform and DSP accelerator.
C6000 devices supported on the SI-C6713DSP card:
TMS320C6713B
A full line of software development tools are available from Sheldon Instruments and TI, which include compilers, assemblers, linkers, and debuggers.
Host PCI bus to DSP Link
The hardware interface betwen the host PCI bus and the DSP is implemented with PLX’s PCI9054 device. Onboard control logic arbitrates the appropriate timing between the C6x’s EMIF bus, the boot SRAM/Flash, and the PCI9054’s local bus.
A combination of hardware and software handshaking takes place in order to support a myriad of data transfer schemes, where the host side can be selected to operate in one mode and the DSP in another. From the host PCI side, three (3) modes are available: 1) target/slave mode, 2) PCI initiated bus mastered transfer mode with the PCI9054 acting as the bus master, and 3) bus mastering with the DSP acting as the PCI bus master. From the DSP side, three (3) modes are available: 1) standard programmed I/O, 2) asynchronous DMA, and 3) synchronous DMA.
Host target/slave mode accesses are performed when the DSP is either disabled (reset asserted) or enabled (reset deasserted). While the DSP is disabled, the host uses target/slave mode transfers to load an initialization COFF file to the card’s boot SRAM/Flash memory, as well as to access expansion daughter modules. After DSP activation, any combination of data transfer modes can be used on either side.
For most applications, the most efficient method of large data block transfer is to use PCI bus mastering, as it requires minimal host intervention. The first bus master method involves using the PCI9054’s DMA engine, in conjunction with the DSP using programmed I/O or its own DMA engine. The second bus master transfer method allows the DSP to act as the PCI bus master, where it actually has direct access to the host computer’s main memory.
Memory Options
The SI-C6713DSP is configured with conventional 144 pin SO-DIMM socket to accommodate standard, 3.3V non-buffered PC133 SDRAM modules used in laptops. The SI-C6713DSP-PCI supports *half* of the capacity on 64MB, 128MB, 256MB, and 512MB module sizes, making it a very cost effective solution for the most demanding and memory intensive applications.
Form Factors & Hardware Expansion
The SI-C6713DSP are offered in a variety of PCI bus form factors such as desktop PCI, PCI-104, PMC, and CompactPCI. All of them include expansion connectors allowing for custom designs, or for attaching ‘off the shelf’ multifunction I/O modules from Sheldon Instruments. Sheldon Instruments offers several daughter modules for multichannel analog and digital I/O, including 4 to 64 channels of 16 bit ADCs and DACs.
The SI-C6713DSP is available with extensive development tools from Sheldon Instruments and TI.
For quick turnkey development, Sheldon Instruments offers QuVIEW and QuBASE, which are a set of DSP-resident libraries for real time performance that greatly accelerate data acquisition, signal processing, and control applications. QuVIEW is a real time accelerator for LabVIEW, and QuBASE a real time accelerator for Visual Basic. A full range of examples and tutors are provided to demonstrate their ease of use and breadth of functionality and capabilities. QuBASE runs under Windows, while QuVIEW also runs under Linux.
When purchased as a DSP evaluation board, Sheldon Instruments also includes free sample DSP and Windows or Linux 32/64 bit device driver source code to accompany TI’s CCS development environment. The DSP source code illustrates full communication modes, and the Windows or Linux device driver source code includes the complete SI-DDK, along with COFF file loader utilities.
C6713 Processor Resources
For more detailed documentation, check out the SI-C671x Wiki Homepage
Important information for developers that program the DSP in C or Assembler is available from Texas Instrument’s website (QuVIEW and QUBASE users usually do not need these details).
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Link, Description
TMS320C6713 Product Folder, Your main resource with links to data sheets; feature lists; user guides; application notes and software.
TMS320C67x DSP Library, A free-of-charge optimized floating-point DSP Function Library for C programmers using the C67x devices. It includes C-callable; assembly optimized general purpose signal processing routines. These routines are typically used in computationally intensive real time applications where optimal execution speed is critical. By using these routines; you can achieve execution speeds considerably faster than equivalent code written in standard ANSI C. In addition; by providing ready-to-use DSP functions; the TI DSPLIB can significantly shorten your DSP application development time.
TMS320C67x Fast RTS Library, The C67x FastRTS is a collection of optimized floating-point math functions for C programmers using the C67x devices. Both single and double precision floating point versions of these functions are available.
TMS320C6000 Chip Support Library, The Chip Support Library (CSL) provides an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use; compatibility between various C6000 devices; and hardware abstraction. This will shorten development time by providing standardization and portability. The functions listed in the features section are specifically designed for all the C6000 DSPs; including the C6713.
3rd Party Software, TI has a variety of software available that enables quick movement through the DSP application design process. Some of this software is free of charge; some needs to be purchased.
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Processor for SI-C6713DSP
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TI 300MHz TMS320C6713[attr colspan=”2″]
MIPS/MFLOPS, 2400/1800
DMA Channels, 16 (2 dedicated for PCI bus)
L1 Program Cache/SRAM, 4KB
L1 Data Cache/SRAM, 4KB
L2 Cache/SRAM, 256KB
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External Memory
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SDRAM Memory[attr colspan=”2″]
Type/Speed, Standard 3.3V; non-buffered PC133 SO-DIMM module clocked from DSP’s E Clock running at 75Mhz
Sizes[attr rowspan=”2″], 64MByte (16Mx32)
256MByte (64Mx32)
Mapping[attr rowspan=”2″], CE2: DSP memory region starting at 0xA0000000
CE3: DSP memory region starting at 0xB0000000
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[table class=”siTB”]
Boot Memory[attr colspan=”2″]
Type/Size, 512kx8 SRAM or 2Mx8 NOR Flash memory
Configuration, Dual Access memory: Accessible by host (only while DSP is inactive/reset) for downloading COFF files. Accessed by DSP during its boot loading process
Mapping, CE1: DSP memory region starting at 0x90000000
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Interfaces
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PCI Interface between Host PC and DSP[attr colspan=”2″]
Active Communication Modes[attr rowspan=”2″], Data Transfers: Bus master DMA and target mode
Messaging with user defined mailboxes
Transfer Rates[attr rowspan=”2″], Burst Transfers: Up to 132Mbyte/sec with block sizes of eight (8) 32 bit words
Sustained Transfers: Up to 12Mbyte/sec with any block size using DMA
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Connectors
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Port Connectors[attr colspan=”2″]
PCI[attr rowspan=”4″], Desktop PCI: One Edge connector
PCI-104: One 120 pin (2mm 4×30) stacking connector
3U CompactPCI: One 110 pin (2mm 5×22) Type A Backplane connector
PMC: Two 64 position Mezzanine connector
JTAG, One 14 pin (2×7) header
EMIF (DSP Expansion), One 150 pin (2mm 5×30) Peripheral Expansion connector
GPIOs & Timers (Desktop PCI only)[attr rowspan=”2″], One 50 pin (2×25) header: McBSP1 – TINP[1:0] – TOUT[1:0]
One 10 pin (2×5) header: McBSP0
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Peripheral Expansion[attr colspan=”2″]
DSP Expansion[attr rowspan=”2″], First external 2mm pitch: 150 pin (5×30) socket connector for interfacing the expansion module to all of the DSP’s peripheral ports (EMIF – McBSP – McASP – HPI/GPIO – Timers)
DSP EMIF bus: Isolated using LVC2245 buffers. Decodes 64kx32 words mapped on CE1 with Address (A[15:0]); Data (D[31:0]); Control (X_R/Wn – X_CSn – X_INT[1:0] – X_RDY – X_CLK[1:0]); and Power (3.3V; +/-12V; 5V; 1.8V)
User I/O[attr rowspan=”2″], Externally accessible user I/O 100 pin connector: half pitch (0.050″); Series III DSUB for interfacing external user defined signals to the 2mm User I/O connector. AMP part 787169-9; 787170-9; or 787362-9
Second external 2mm pitch: 120 pin (4×30) socket connector for interfacing external user defined signals to custom daughter module. Linked only to externally accessible 100 pin half pitch DSUB connector
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Mechanical Properties
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Physical Dimensions/Electrical Requirements/Temperature[attr colspan=”2″]
Form Factor Dimensions[attr rowspan=”4″], Desktop PCI (3/4 size): 9″/23cm(L) x 4.9″/12.5cm(W)
PCI-104: 3.55″/9.02cm(L) x 3.775″/9.59cm(W)
3U CompactPCI: 6.3″/16cm(L) x 3.94″/10cm(W)
PMC: 5.86″/14.9cm(L) x 2.9″/7.4cm(W)
Weight, 0.31lbs/140 grams
Supply Voltages, +3.3Vdc @ 1.5A; ±12Vdc supplies passed on to expansion connector and not used by onboard circuitry
Power, 4.5 Watts typical with 128MB SDRAM
Temperature, Commercial grade 0º-85ºC. Consult factory for availability of industrial and military temperature grades
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PCI Form Factor
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Product, Description, Price (US dollars)
SI-C6713DSP-PCI-64, 64MB SDRAM – 300Mhz DSP – 512Kx8 Boot SRAM, 1985
SI-C6713DSP-PCI-256, 256MB SDRAM – 300Mhz DSP – 512Kx8 Boot SRAM, 2110
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PCI-104 Form Factor
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Product, Description, Price (US dollars)
SI-C6713DSP-PCI104-64, 64MB SDRAM – 300Mhz DSP – 512Kx8 Boot SRAM, 1985
SI-C6713DSP-PCI104-256, 256MB SDRAM – 300Mhz DSP – 512Kx8 Boot SRAM, 2110
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3U CompactPCI Form Factor
[table class=”siTB”]
Product, Description, Price (US dollars)
SI-C6713DSP-cPCI-64, 64MB SDRAM – 300Mhz DSP – 512Kx8 Boot SRAM, 2085
SI-C6713DSP-cPCI-256, 256MB SDRAM – 300Mhz DSP – 512Kx8 Boot SRAM, 2210
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PMC Form Factor
[table class=”siTB”]
Product, Description, Price (US dollars)
SI-C6713DSP-PMC-64, 64MB SDRAM – 300Mhz DSP – 512Kx8 Boot SRAM, 2085
SI-C6713DSP-PMC-256, 256MB SDRAM – 300Mhz DSP – 512Kx8 Boot SRAM, 2210
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