SI-66AK2xx Board
A powerful Keystone II Multicore ARM + Digital Signal Processor (DSP) card for the PCIe bus.


The SI-66AK2xxDSP from Sheldon Instruments is a C programmable ARM plus Digital Signal Processor (DSP) card designed for low power environments that require intensive computing in a cost sensitive solution.

Keystone II devices supported on the SI-66AK2xxDSP card:
66AK2H14 (4 ARM + 8 DSP CorePacs)
66AK2H12 (4 ARM + 8 DSP CorePacs)
66AK2H06 (2 ARM + 4 DSP CorePacs)
66AK2L06 (2 ARM + 4 DSP CorePacs)

The 66AK2xDSP-PCIe is a Small Form Factor (SFF) family of Commercial Off the Shelf (COTS) cards featuring the powerful Keystone II 66AK2xx ARM plus DSPs from Texas Instruments. The TI 66AK2xx devices are multicore ARM + DSP System on Chip (SoC), conveniently programmed using the C language. There are separate ARM and DSP subsections, with the ARM subsection consisting of two to four A15 cores clocked at 1.4GHz for a maximum of 192,000 MIPS, and with the DSP subsection consisting of four to eight C667x CorePacs clocked at 1.2GHz for a maximum of 352 GMAC performance. All of this is attained at a mere 14 watts of power consumption while most processors of this caliber are in the 60W range.

The ARM subsection features 32K Bytes of L1 per core and 4M Bytes of shared L2 on internal memory. Each CorePac of the DSP subsection features 32K Bytes L1P, 32K Bytes L1D, and 1M Bytes of L2. Each level of cache can be programmed in blocks as SRAM or cache. The 66AK2xx chip also features a memory controller that arbitrates 6M Bytes of shared SRAM memory between all cores of both subsections, along two external 64-bit DDR3 memory interfaces at 1600MHz.

High Speed Serial Interfaces: GbE, PCIe, & SRIO
There are multiple high speed interfaces, with each capable of moving large amounts of data. The Gigabit Ethernet interface can take advantage of the on-chip Network Co-processor to offload most of the packet processing, thereby enabling full bandwidth utilization and freeing up the ARM+DSPs to perform the computations for which they were designed. A PCIe x2 Gen 2.0 interface provides connectivity to a system backplane or Thunderbolt cable, and the flexible SRIO 2.1 x4 5Gbps interface can be connected to either an optional FPGA or other external peripherals. Separately, the 66AK2H14 also features a 10 Gigabit Ethernet switch subsystem.

Hardware Expansion with FPGA & FMC
The optional Altera Cyclone V FPGA includes SI’s proprietary IP layer that transparently translates SRIO so the FPGA may be used as an extra processing resource, as well as an expansion bridge to either an FPGA Mezzanine Card (FMC), or a legacy style parallel expansion bus – ideal for those who prefer to leverage a wide array of 3rd party FMC modules, their own custom hardware or simply update legacy designs with minimal effort.

Upgrade options for the SI-66AK2xxDSP include various core and memory configurations, nonvolatile storage, and either commercial or expanded temperature ranges. A full line of software development tools are available from Sheldon Instruments and TI for Windows and Linux platforms.


  • Real Time Image Processing
  • Machine Vision
  • Unmanned Aerial Vehicle Control Systems
  • Industrial Control and Automation
  • Additive Manufacturing
  • Medical Imaging
  • Military and Aerospace
  • Test and Measurement

Block Diagram

PCIe-104 Diagrams

The SI-66AKH2xDSP is available with extensive development tools from Sheldon Instruments and TI for both the host PC side as well as the DSP side.

Host Side Tools
For the host PC side, Sheldon Instruments provides Windows/Linux 32/64 bit drivers, along with comprehensive sample application projects, with easy to use API libraries and related source code. The sample projects will be supplied as a command line utility, with a companion Qt GUI version. Its functionality includes:

  • Load ELF/EABI files created from TI’s Code Composer Studio (CCS) to any one of the user specified cores, and also enable the core to execute its program.
  • Comprehensive communications with read and write functionality to demonstrate single register, a register array, and DMA accesses.
  • A messaging scheme will be implemented allowing for either the host PC or the DSP to alert the other for user defined asynchronous events.

DSP Side Tools
For the DSP side, TI tools include Code Composer Studio Integrated Development Environment (CCS), and the Multicore Software Development Kit (MCSDK) that includes the Board Support Package (BSP), Chip Support Library (CSL), Network Development Kit (NDK), and Sys/Bios. Sheldon Instruments provides various TI CCS projects for the DSP, both compiled versions for quick loading with the host side sample program, along with complete projects and related source code. These DSP projects include:

  • A bare low-level runtime initializer to demonstrate how to setup DSP entry points.
  • A project to demonstrate TI SYS/Bios usage and initialization.
  • Various projects to demonstrate initialization and usage of the C667x system components. In particular, configuration of the DDR3 module, Ethernet (with a stack or using the packet accelerator), EDMA3 transfers, and the Onchip Interrupt Controller.

Keystone II 66AKH2x Processor Resources
For more detailed software documentation, check out the SI-C667x Keystone I Wiki Homepage.

There is important information for developers available from Texas Instrument’s website.

Processor for SI-66AK2xxDSP
[table class=”siTB”]
TI Keystone II 66AK2xx Family[attr colspan=”3″]
Number of Cores[attr rowspan=”2″], 66AK2H06 and 66AK2L06, 2 ARM + 4 DSP
66AK2H12 and 66AK2H14, 4 ARM + 8 DSP
DSP Subsection (each C667x CorePac)[attr rowspan=”5″], Clocking, 1.2GHz
GMACS/GFLOPS, 38.4/19.2
L1 Program Cache/SRAM, 32KB
L1 Data Cache/SRAM, 32KB
L2 Cache/SRAM, 1MB
ARM Subsection (each Cortex A15 core)[attr rowspan=”4″], Clocking, 1.4GHz
MIPS, 9800
L1 Instruction and Data Cache/SRAM, 32KB
Shared L2 Cache/SRAM, 4MB
Shared[attr rowspan=”1″], L2 Cache/SRAM, 6MB


External Memory
[table class=”siTB”]
DDR3 Memory[attr colspan=”3″]
Port A[attr rowspan=”2″], Size, 2GB (256M x 64)
Speed, 1600Mhz
Port B (66AK2Hxx only)[attr rowspan=”2″], Size, 2GB (256M x 64)
Speed, 1600Mhz


[table class=”siTB”]
Storage / Nonvolatile Memory[attr colspan=”2″]
SPI[attr rowspan=”2″], up to 64Mbit (8Mbx8) Flash
microSD flash card
I2C, up to 2KB EEPROM (inside Tiva uC)


Optional Altera Cyclone 5 GX FPGA
[table class=”siTB”]
Resource, C3, C4, C5, C7, C9
Logic Elements (LE) (K), 31.5, 50, 77, 149.5, 301
ALM, 11900, 18868, 29080, 56480, 113560
Register, 47600, 75472, 116320, 225920, 454240
M10K, 1190, 2500, 4460, 6860, 12200
MLAB, 159, 295, 424, 836, 1717
Variable-preicision DSP Block, 51, 70, 150, 156, 342
18 x 18 Multiplier, 102, 140, 300, 312, 684
PLL, 4, 6, 6, 7, 8
SRIO Lanes @ 3.125Gbps, 2, 4, 4, 4, 4


Other Altera, Xilinx or Lattice devices also available on special request.

High Performance Serial Interfaces

[table class=”siTB”]
Interface, Lanes, Speed
PCI Express Gen2[attr rowspan=”3″], Desktop PCIe: 2, 5 Gbps[attr rowspan=”3″]
PCIe-104: 1 or 2
Thunderbolt: 2
SRIO rev2.1 (66AK2Hxx only), 4, 5 Gbps
Gigabit Ethernet, 1, 10/100/1000 Mbps
10 Gigabit Ethernet (66AK2H14 only), 1, 10 Gbps
Hyperlink (66AK2Hxx only), 4, 12.5 Gbps


Port Connectors

[table class=”siTB”]
Port, Count, Connector Style
PCIe Gen 2[attr rowspan=”2″], 1[attr rowspan=”2″], Desktop PCIe: Edge connector (Endpoint)
PCIe-104: 3 segment Samtec QMS (Root Complex or Endpoint)
Ethernet, 2, RJ45s with integrated magnetics and LED indicators
microSD, 1, Standard socket for microSD/SPI flash
JTAG, 1, Keyed 14 pin (2×7) header; compatible with all third party emulators and debuggers
Optional Hyperlink (66AK2Hxx only)[attr rowspan=”2″], 1[attr rowspan=”2″], Desktop PCIe: Optional mini-SAS HD+ 4i socket connector (Molex part number 76867-001; Mating cable is Molex 1110670200)
PCIe-104: Optional Searay connector to stack another SI-DSP carrier also equipped with a Hyperlink port
Optional Buffered UART, 1, 6 pin header
microUSB (Tiva uC), 1, microAB for card configuration


[table class=”siTB”]
Optional Peripheral Expansion[attr colspan=”2″]
SRIO x1 lane Expansion (66AK2Hxx only), Single segment QMS connector
FMC/Parallel Expansion (available with FPGA only), FMC connector


Mechanical Properties
[table class=”siTB”]
Physical Dimensions/Electrical Requirements/Temperature[attr colspan=”2″]
Form Factor Dimensions[attr rowspan=”2″], Desktop PCIe (3/4 size): 9″/23cm(L) x 4.9″/12.5cm(W)
PCIe-104: 4.55″/11.6cm(L) x 3.775″/9.59cm(W)
Weight, 0.31lbs/140 grams
Supply Voltages, 3.3V @ 0.75A and +12V @ 1.5A
Power, 20 Watts typical; up to 28W with optional FPGA
Temperature, Commercial grade 0-85C. Consult factory for availability of industrial and military temperature grades


PCIe Form Factor Cards
[table class=”siTB”]
Product, Description, Price (US dollars)
SI-66AK2H14DSP-PCIe, 66AK2H14 – 4 ARM + 8 DSP CorePacs, Call
SI-66AK2H12DSP-PCIe, 66AK2H12 – 4 ARM + 8 DSP CorePacs, Call
SI-66AK2H06DSP-PCIe, 66AK2H06 – 2 ARM + 4 DSP CorePacs, Call
SI-66AK2L06DSP-PCIe, 66AK2L06 – 2 ARM + 4 DSP CorePacs, Call


PCIe-104 Form Factor Cards
[table class=”siTB”]
Product, Description, Price (US dollars)
SI-66AK2H14DSP-PCIe, 66AK2H14 – 4 ARM + 8 DSP CorePacs, Call
SI-66AK2H12DSP-PCIe, 66AK2H12 – 4 ARM + 8 DSP CorePacs, Call
SI-66AK2H06DSP-PCIe, 66AK2H06 – 2 ARM + 4 DSP CorePacs, Call
SI-66AK2L06DSP-PCIe, 66AK2L06 – 2 ARM + 4 DSP CorePacs, Call


FPGA Options
[table class=”siTB”]
Product, Description, Price (US dollars)
-C3, x2 SRIO @ 3.125Gbps – 31k Gates, Call
-C4, x4 SRIO @ 3.125Gbps – 50k Gates, Call
-C5, x4 SRIO @ 3.125Gbps – 77k Gates, Call
-C7, x4 SRIO @ 3.125Gbps – 149k Gates, Call
-C9, x4 SRIO @ 3.125Gbps – 301k Gates, Call