SI-MOD32xx
  • SI-MOD32xx
  • SI-MOD32xx
The SI-MOD32xx FMC Expansion I/O Module.

Description

The SI-MOD32xx is a family of high resolution, FMC form factor, high channel count multi function data acquisition and control modules that plug into any SI-DSP or FPGA carrier card.

  • Up to 4 parallel ADC circuits; each with 8SE/4DE Analog Inputs (32SE/16DE maximum), 1Mhz sampling, 16 bit resolution, 1-10 gains.
  • Up to 2 parallel DAC circuits; each with 8 Analog Outputs (16 maximum), 250khz update rates, 16 bit resolution.
  • On board 32KByte EEPROM contains offset/gain errors, loaded to FPGA for real time digital calibration on all analog I/O.
  • 2 ports of 16 bit digital I/O (32 lines total).
  • FMC single width 84mmx69mm form factor, High Pin Count (HPC), 2.5V-3.3V LVCMOS signal levels.
  • Software development tools from Sheldon Instruments included with the SI-DDKs; as well compatibility with separately purchased FPGA and third party tools.
  • Windows and Linux 32/64 bit drivers and sample application support.

Analog Inputs
Each card features up to four (4) parallel ADC circuits, each with up to 8SE/4DE analog input channels where the total count may add up to 8SE/4DE, 16SE/8DE or 32SE/16DE. Each ADC circuit is comprised of its own multiplexer, programmable gain instrumentation amplifier and ADC. Up to four (4) distinct channels, one from each circuit, can be simultaneously sampled. Each ADC’s resolution is 16 bits with sampling rates ranging from 0hz to 1Mhz. The high impedance input voltage level is between +/-10Vp, with gains ranging from 1, 2, 4, 10. The ADCs are based on a Successive Approximation architecture, which makes them ideal for control applications. Each input’s termination can be individually programmed for single or differential ended operation, thereby not limiting you to an all-or-nothing configuration.

Analog Outputs
There’s the option of two (2) parallel DAC circuits with eight (8) analog outputs each, where the total count may add up to sixteen (16) channels. The DAC resolution is 16 bits, and can update at rates up to 250khz per channel. The outputs are programmable as either unipolar with ranges of 0V-2.5Vp, 0V-5Vp, or 0V-10Vp, or bipolar with ranges of +/-5Vpp or +/-10Vpp.

Digitally Controlled Calibration
An on board 32KByte EEPROM contains the offset and gain errors which are loaded into the DSP or FPGA and used to implement real time digital calibration on all analog I/O.

Digital I/O
Thirty two (32) general purpose, highly flexible digital I/O lines may be configured as bidirectional, buffered 16 bit ports. These lines are in addition to any of the digital I/O lines native to the SI-DSP or FPGA carrier card.

FMC-HPC Interface
The flexible FMC High Pin Count (HPC) interface allows for maximum flexibility for clocking and control, with 2.5V-3.3V LVCMOS signal levels to interface to all ADCs, DACs, and digital IO buffers.

Applications

  • Unmanned Aerial Vehicle Control Systems
  • Industrial Control and Automation
  • Additive Manufacturing
  • Military and Aerospace
  • Test and Measurement


SI-MOD32xx Block Diagram

SI-DSP + SI-MOD Slot & Stackup Arrangement Diagrams


All functions for the SI-MOD32xx are fully programmable via the HPC interface, with support files for Altera or Xilinx FPGAs (Lattice supplied upon request).

For more detailed documentation, check out the SI-MOD32xx Wiki Homepage


Connectivity

Expansion Interface
FMC Interface High Pin Count; 2.5V-3.3V LVCMOS signaling
Clock Speed up to 50Mhz

 


Analog Inputs

Analog Input Section
Input Termination SI-MOD3208: 8S/4D; 0hz to 1Mhz additive sampling for all channels
SI-MOD3216: 16S/8D; 0hz to 2Mhz additive sampling for all channels
SI-MOD3232: 32S/16D; 0hz to 4Mhz additive sampling for all channels
Flexible Input Termination; each channel individually programmable for differential or single ended operation
Input Characteristics Voltage Level: +/-10Vp maximum
Impedance: minimum 1Mohm
Coupling: DC
Fully Integrated MUX-PGA-ADC Circuitry p/n ADAS3022 (Analog Devices)
Mux: 8SE/4DE channels
PGA: 1; 2; 4; 10
ADC: Succesive Approximation ADC; 1Mhz @ 16 bits

 

Analog Outputs

Optional Analog Output Section
Options -8DAC: 8 Analog Outputs
-16DAC: 16 Analog Outputs
DAC Circuit p/n LTC2666 (Linear Technology)
Update Rate 0hz to 250khz per channel
Programmable Output Voltage Level Bipolar: +/-2.5Vp; +/-5Vp; +/-10Vp
Unipolar: 0V-5V; 0V-10V

 

Digital I/O

Digital I/O Section
32 General Purpose Discrete I/O 32 line bi-directional port with programmable directional control as two individual 16 bit ports. Nominal 3.3V CMOS/TTL logic levels; directly tied to 74LVC2652 class of bidirectional buffers

 


General Features

General Features
FMC with HPC Interface
On board 32KByte EEPROM contains offset/gain errors; loaded to FPGA for real time digital calibration on all analog I/O
Full suite of development tools from Sheldon Instruments
Windows and Linux 32/64 bit application and driver support

 


Mechanical Properties

Physical Dimensions/Electrical Requirements/Temperature
Dimensions single width: 3.3″/8.4cm(L) x 2.7″/6.9cm(W)
Weight 0.18lbs or 85 grams
Supply Voltages Vadj: 2.5V-3.3V for FMC interface circuitry
12Vdc: Used to generate +/-15Vdc for analog circuitry; 5Vdc for analog and digital IO buffers.
Power 2 Watts typical with minimum configuration: +15Vdc@0.04A; -15Vdc@0.04A; 5Vdc@0.12A; Vadj@0.033A
7 Watts typical with maximum configuration: +15Vdc@0.17A; -15Vdc@0.17A; 5Vdc@0.12A; Vadj@0.033A
Temperature Commercial grade 0-85C. Consult factory for availability of industrial and military temperature grades

 


Multifunction I/O Module with 1MHz ADCs

Product Description Price (US dollars)
SI-MOD3208 4D/8S analog in – x1 SAR 16 bit ADC @1Mhz – gains 1 to 10 – 32 digital I/Os TBD
SI-MOD3216 8D/16S analog in – x2 SAR 16 bit ADC @1Mhz – gains 1 to 10 – 32 digital I/Os TBD
SI-MOD3232 16D/32S analog in – x4 SAR 16 bit ADC @1Mhz – gains 1 to 10 – 32 digital I/Os TBD

 

DAC Options for SI-MOD32xx

Option Description Price (US dollars)
-8DAC Add “-8DAC” to part number. x8 analog outputs TDB
-16DAC Add “-16DAC” to part number. x16 analog outputs TBD