SI-C6713DSP DSP Software Guide

SI-C6713DSP Block Diagram

SI-C6713DSP Block Diagram

Host Side Mapping

The PC I Base Addresses (BADDR) are automatically assigned by the host at boot time, with the requested resources as outlined in the following table:

Common Resources & Mapping
PCI BADDRnRange (Bytes)ResourceHost BADDRn+Offset (Byte Boundary)DSP External CEnDSP Base Address (Byte Boundary)
n/a64K-2MAdd-on Init Buffer (DSP Side Only)n/a00x8000,0000~0x801F,FFFF
0256PLX OpRegsMemory Mapped0x00~0xFF0x8034,0000~0x8034,00FF
1I/O Mapped (unused)
28MFPGA: 2x 32 Deep FIFO0x00,0000~0x0F,FFFF0x8020,0000~0x802F,FFFF
FPGA: x64 Comm Regs0x10,0000~0x13,FFFF0x8030,0000~0x8033,FFFF
FPGA: x12 CSRsCSR11: 0x10,0100~0x10,40FF0x8030,0100~0x8030,40FF
CSR[0:10]: 0x14,0000~0x1B,FFFF0x803C,0000~0x803C,FFFF
Expansion Module (64Kx32)0x1C,0000~0x1F,FFFF0x8038,0000~0x803B,FFFF
BootMEM (SRAM=512kx8SRAM/NOR=1Mx16)0x20,0000~0x7F,FFFF10x9000,0000~0x9FFF,FFFF

DSP Side Mapping

The DSP's resource access is split between onchip SRAM along with the external memory interface (EMIF). The EMIF is partitioned into four separate pages, with varying depths per page. Each page is externally identified in hardware with the CE[3:0] signals. Please consult the C6x's documentation for more details:

DSP Mapping
DSP SpaceResourceUsed Physical Range (DWord)DSP Base Address (Byte Boundary)
OnchipInternal SRAML2: 192k0x0000,0000-0x0002,FFFF
Cache: 64k0x0003,0000-0x0003,FFFF
External CEn0Add-on Init Buffer (DSP Only)16K-512K0x8000,0000-0x801F,FFFF
FPGA: 2x32 FIFO10x8020,0000
FPGA: CommRegs640x8030,0000-0x8030,00FF
PLX Registers640x8034,0000-0x8034,00FF
Expansion Module64k0x8038,0000-0x803B,FFFF
FPGA: CSRs5CSR11: 0x8030,0100-0x8030,0103
CSR[0, 3, 8, 9]: 0x803C,0000-0x803C,C000
1BootMEMSRAM: 512Kx80x9000,0000-0x9FFF,FFFF
NOR Flash: 1Mx16 (Optional)
332MB~128MB (Optional)0xB000,0000-0xBFFF,FFFF