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SI-C667xDSP DSP Hardware Guide

DSP Overall Architecture

The SI-C667xDSP carrier card has TI's Keystone I C667x DSP, along with an optional Intel-Altera Cyclone V GX FPGA which serves as a bridge between the DSP and the FMC expansion port.

For the DSP side, please refer to the specific TI Keystone DSP datasheet for details on the architecture of the device placed on the SI-C667xDSP board.
One Core:
http://www.ti.com/lit/ds/symlink/tms320c6671.pdf
Two Cores:
http://www.ti.com/lit/ds/symlink/tms320c6672.pdf
Four Cores:
http://www.ti.com/lit/ds/symlink/tms320c6674.pdf
Eight Cores:
http://www.ti.com/lit/ds/symlink/tms320c6678.pdf

Clocking

An external CDCM6208-V1 clock generator feeds the DSP's internal PLLs. These PLLs subsequently generate the necessary clocks which are set for the following defaults, but may be altered depending on applications requirements.

External Clock Generator Fed to DSP	Internal DSP PLL Setting	Comments
CORE_Clk = 100Mhz	SYSCLK1 (Main) = 1Ghz	Max = 1.25Ghz
DDR3_Clk = 50Mhz	DDR3 = 665Mhz/1.3Ghz	Max = 666.7Mhz/1.33Ghz
PASS_Clk: Core_Clk = 100Mhz	PASS = 1Ghz	Max = 1.25Ghz
SRIO-SGMII_Clk = 250Mhz	SerDes = 2.5Ghz	Max = 3.125Ghz
PCIE_Clk = 100Mhz	PCIe Gen1 SerDes = 2.5Gbps	Gen2 Max = 5Gbps
MCM_Clk = 0hz	Hyperlink PLL = not used

Internal DSP Main PLL Controller SYSCLKs
PLL Divider Value	SYSCLKn Nominal Rate	Max Rate
1	SYSCLK1 = 1Ghz	Max = 1.25Ghz
x	SYSCLK2 = xMhz	Max = xMhz
2	SYSCLK3 = 500Mhz	Max = 625Mhz
3	SYSCLK4 = 333.33Mhz	Max = 416.67Mhz
y	SYSCLK5 = yMhz	Max = yMhz
64	SYSCLK6 = 15.625Mhz	Max = 19.53Mhz
6	SYSCLK7 = 166.67Mhz	Max = 208.33Mhz
z	SYSCLK8 = zMhz	Max = zMhz
12	SYSCLK9 = 83.33Mhz	Max = 104.67Mhz
3	SYSCLK10 = 333.33Mhz	Max = 416.67Mhz
6	SYSCLK11 = 166.67Mhz	Max = 208.33Mhz

Memory

Memory Mapping

Listed below are the key memory regions on the Keystone device.

Internal L2 RAMs
Base Address: 0x1n80_0000 (n is the core number).
L2 RAM local address for each core is 0x80_0000.
To access L2 RAMs externally, add 0x1n00_0000 to the local address.
For example, the L2 RAM of core 0 is accessed with a program running on core 0 when referencing 0x80_0000 or 0x1080_0000. On the other hand, the L2 RAM of core 1 is accessed when referencing 0x1180_0000.

Shared Internal DSP Memory
Base Address: 0x0C00_0000
There is a shared 4MB (64k x 64 bits) internal memory region for all cores on the C667x platform, with lower access latency than the external DDR3 memory used for running programs on one or more DSP cores.

External DSP DDR3 Memory
DDR3 Config Base Address: 0x2100_0000.
DDR3 Data Base Address: 0x8000_0000.
The external 64 bit DSP DDR3 is clocked at the full 667Mhz (effective 1333Mhz data rate), with a capacity totalling 512MB (64Mega x 64 bits), and expandable to 2GB (256Mega x 64 bits).

For information regarding other hardware modules and registers, please refer to the Overall Architecture and TI User's Guide of each individual module. There is highly useful information regarding the performance of accessing different memory regions within the C667x platform:
https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/135086

EDMA3

The enhanced direct memory access (EDMA3) controller’s primary purpose is to service data transfers between two memory-mapped slave endpoints on the SI-C667xDSP boards.
Please refer to TI's EMDA3 user's guide for more details:
http://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf

High Speed Serial Links

PCIe

PCIe Config Base Address: 0x2180_0000.
PCIe Data Base Address: 0x6000_0000.
Please refer to TI's PCIe wiki and user's guide for more details of C667x's PCIe x2 lane, 5Gbps core module:
http://processors.wiki.ti.com/index.php/PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices
http://www.ti.com/lit/ug/sprugs6d/sprugs6d.pdf

SRIO

SRIO Config Base Address: 0x0290_0000.
The x4 lane 3.125Gbps-5Gbps SRIO SerDes port is used as a link between the DSP and the Optional expansion FPGA and FMC interface.
Please refer to DSP SRIO->FPGA section as well as TI's SRIO user's guide for more details:
http://www.ti.com/lit/ug/sprugw1c/sprugw1c.pdf

Ethernet

There are two Gigabit Ethernet ports available on the SI-C667xDSP carrier card. Please refer to the GbE switch subsystem document:
http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf

Listed below are the hardware submodules related to the Ethernet interface on the Keystone device.

NETCP (NetWork Coprocessor)
NETCP Base Address: 0x0200_0000.
The NETCP is the interface between the external Ethernet PHY and other internal modules.

QMSS (Queue Manager Subsystem)
The QMSS is a queue for buffering packets.

CPPI (Communications Port Programming Interface)
The CPPI is an interface that re-directs packets to the destination module from the QMSS. More details can be found in the following document:
http://www.ti.com/lit/ug/sprugr9h/sprugr9h.pdf

PA (Packet Accelerator)
The PA is a submodule inside the NETCP which can filter out packets in hardware. More details can be found in the following document:
http://www.ti.com/lit/ug/sprugs4a/sprugs4a.pdf

These terms may seem complicated and overwhelming at first glance, but intimate knowledge of these modules is not required.

The TI NDK is an easy-to-use framework for network programming on the Keystone DSP and hides most of the low-level details. However, to achieve better network perform and lower latency, the TI LLDs of each module listed above should be used instead of the NDK. Sample_Ethernet provides sample configurations of the QMSS, CPPI and PA modules. In any case, to use them effectively please refer to their respective User's Guide.

Legacy Serial Links

UART

UART Base Address: 0x0254_0000.
A single full duplex, buffered 3.3V UART port is available on the SI-C667xDSP carrier card. It may be directly connected to a UART->USB converter cable to link up to a host computer's USB port, or indirectly to a host computer's RS-232 port by using a separate UART->RS-232 translation circuit. Please refer to the UART user guide:
https://www.ti.com/lit/pdf/sprugp1

The table below lists the DSP's UART connectivity to a 6 pin header:

DSP UART to 6 Pin Header Pinout
UART Line	6 Pin Header
GND	1
-	2
-	3
RxD (UART->DSP)	4
TxD (DSP->UART)	5
-	6

Optional SPI

SPI Base Address: 0x20BF_0000.
SPICLK = 55.55Mhz (SYSCLK1 = 1Ghz), max = 69.44Mhz (SYSCLK1 = 1.25Ghz).
NOTE: SPICLK = SYSCLK7÷3 (SYSCLK1÷18)
Please refer to the SPI user guide:
https://www.ti.com/lit/pdf/sprugp2

There are two (2) optional 3.3V SPI access ports available on the SI-C667xDSP carrier card as described below:

Optional uSD Card Socket
An optional uSD socket may be populated upon request.

Optional SPI Flash
An optional SPI NOR flash device may be populated upon request with a maximum capacity of 128Mb (16MB).

Parallel Port

EMIF16

EMIF Config Base Address: 0x20C0_0000.
CE0n Base Address: 0x7000_0000.
CE1n Base Address: 0x7400_0000.
EMIF16 CLK = 166.67Mhz (SYSCLK1 = 1Ghz), max = 200.83Mhz (SYSCLK1 = 1.25Ghz).
NOTE: EMIF16 CLK = SYSCLK1÷6

The 16 bit EMIF16 parallel port is used as a secondary link between the DSP and the Optional expansion FPGA and FMC interface, with an externally accessible range of 64k x 16 bits, mapped on the DSP's CE0 (may be instead set to CE1 upon request). Please refer to DSP EMIF->FPGA section as well as TI's EMIF16 user's guide for more details:
http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf

Boot Mode

By default, the SI-C667xDSP board is configured to boot in I2C master mode to extract initialization data from an NVRAM, which then allows for a flexible extended or secondary boot cycle to be redirected to any DSP submodule or in stand-alone mode. Once booted, SI supplies a utility to allow for any other boot mode to be written into the onboard I2C NVRAM using a dedicated µUSB port, as opposed to manual DIP switches. The overall boot time of the DSP card is within 50msec~75msec.

With the boot mode configuration utility, there are several boot modes available but three default modes to choose from:

I2C Master, then one of two choices:
1. Endpoint PCIe device - default boot mode. The SI-C667xDSP board is configured to boot in I2C master mode, and then immediately redirected to boot with an PCIe port configured as an endpoint device.
2. SPI boot mode. The SI-C667xDSP board is configured to boot in I2C master mode, and then immediately redirected to boot from an SPI NOR flash.
No Boot. Only JTAG, mainly for debugging.

In the case one of the other boot modes are required, please consult factory. For more details, please refer to the main Keystone data sheet sections 2.4, 2.5 and 2.6 (document SPRS691), and Keystone Architecture DSP Bootloader (document SPRUGY5C):
http://www.ti.com/lit/ug/sprugy5c/sprugy5c.pdf

JTAG

In order to debug a DSP project through JTAG, follow the steps outlined below:

Create a new target configuration file by right clicking on the project, new->target configuration file.
Rename the file, and click finish.
Open the newly created target configuration file.
In the 'Connection' dropbox, select the specific JTAG debugger that will be used to connect to the DSP.
In 'Device', select TMS320C6678 as the target device.
Click 'Save' in order to save the hardware setup inside the newly created target configuration file.
Click 'Test Connection'. If the JTAG driver is correctly installed, the connection test should pass successfully.
Click the 'green bug' button to compile the debug version of the project and start a new debug session.
At this point, you can setup breakpoints and step through your project.

More details about JTAG troubleshooting may be found on the TI wiki: http://processors.wiki.ti.com/index.php/Debugging_JTAG_Connectivity_Problems

The two main third party suppliers of JTAG debuggers may also be directly contacted for more support:
http://www.spectrumdigital.com/
http://www.blackhawk-dsp.com/