FPGA Overview

The Optional Intel-Altera Cyclone V GX device is offered in a variety of densities in the 672 pin BGA package, and is connected to the DSP via the primary 3.125Gbps-5Gbps SRIO SerDes port as well as the DSP's secondary 166.67Mhz EMIF 16 bit parallel port. The base part numbers for the Cyclone V GX devices starting with the lowest to highest densities are as follows:

5CGXFC3
5CGXFC4
5CGXFC5
5CGXFC7
5CGXFC9

Please refer to the specific Cyclone V GX FPGA datasheet for details on the architecture of the device placed on the SI-C667xDSP-PCIe board.
General information:
https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html
Datasheets:
https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-v/support.html

FPGA Mapping

NOTES:

1. VIO_A and VREF_A refers to the IO bank voltages and corresponding references for the FMC's LA and HA busses, denoted as VADJ_C2M and VREF_A_M2C respectively in the FMC Standard documentation. Similarlarly, VIO_B and VREF_B refers to the IO bank voltages and corresponding references for the FMC's HB bus.
2. The directionality designation of C2M refers to "Carrier to Mezzanine", while M2C refers to "Mezzanine to Carrier."
3. Bank Voltages for the VIO and VREF rails are jumper selectable, and are defaulted at 2.5V or 3.3V.
4. FMC support signals are routed to Cyclone 5GX FPGA bank 5B with the DSP's EMIF16; FMC's M2C clock pairs [1:0] are routed to FPGA bank 7A in conjunction with the FMC's LA & HA busses, and the FMC's bidirectional clock pairs [3:2] are routed to FPGA banks 6A and 8A respectively.
5. Differential IO pairs are compatible with Bus mode LVDS (check datasheet for FPGA pin directions for serial transceiver mode), HSTL, and Differential SSTL signaling standards.
6. The differential signal bandwidth is limited to 230Mbps in order to support bidirectionality in bus LVDS mode. However, differential signaling speed may be dramatically increased by rerouting the circuit board so that the differential signals on the Cyclone V GX FPGA are unidirectional and known in advance to support serial LVDS transceiver mode, or alternately by upgrading to a much higher grade device (and more expensive) from Altera or Xilinx.

DSP To FPGA Interface

FPGA: Programming and Configuration

One of the main criteria for selecting the Intel-Altera Cyclone V GX series of FPGAs is the availability of the free Lite Edition of the Quartus Prime software development tool, which may be downloaded from Intel's website:
https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/download.html

After project creation and synthesis with the Quartus Prime software, the resulting configuration file (Raw Binary File with extension ".rbf") is loaded into the FPGA by an SI supplied utility run on the DSP. The FPGA is designed to boot in the Passive Serial Mode making it dependent on a processor to quickly load the configuration file, thereby removing the necessity for an onboard configuration EEPROM. The ability to load configuration files via a software utility offers an easy upgrade path by avoiding a reburn of an onboard EEPROM and being forced to reinitiate the configuration process or reboot the system.

DSP To FPGA Physical Links

SRIO Link & Pinout

The x4 lane 3.125Gbps-5Gbps SRIO SerDes port is used as a link between the DSP and the Optional expansion FPGA.

Below is the table outlining the DSP's SRIO port to the FPGA's pinout:

EMIF Bus & Pinout

The 16 bit 166.67Mhz EMIF16 parallel port is used as a secondary link between the DSP and the Optional expansion FPGA (which serves as a bridge to the FMC interface), with an externally accessible range of 64k x 16 bits, mapped on the DSP's CE0 (maybe set instead to CE1 upon request).

Below is the table outlining the DSP's EMIF port to the FPGA's pinout:

GPIOs & Pinout

Four DSP GPIOs may be used as FPGA-> DSP interrupts or as user defined general purpose lines.

Below is the table outlining the FPGA's pinout to the DSP's GPIO port:

FMC Interface & Expansion

The expansion site incorporates the widely adopted FMC standard, which allows for the integration of either the SI-MOD32xx-FMC module, a wide variety of most third party LPC modules (and some HPC modules, please consult SI in order to evaluate compatibility), or a custom module design where SI will provide all of the necessary support for successful project completion.

The FPGA serves as a bridge between the DSP and the FMC expansion site with these general properties and user defined I/O signals:

• Single Width FMC site (HPC 400 pin connector).
• Bank Voltages for the VIO and VREF rails are jumper selectable.
• User defined IOs, for a total of 80 differential pairs or 160 single ended IOs:
  1. Complete LA bus: 34 differential IO pairs or 68 single ended IOs (compatible with LPC modules).
  2. Complete HA bus: 24 differential IO pairs or 48 single ended IOs (compatible with HPC modules).
  3. Complete HB bus: 22 differential IO pairs or 44 single ended IOs (compatible with HPC modules).
• Clock pairs:
  1. Qty. 2 differential clock pairs [1:0] from Mezzanine to Carrier.
  2. Qty. 2 differential bidirectional clock pairs [3:2].
• FMC support signals for power monitoring and presence of FMC module.
• Miscellaneous support lines:
  1. Qty. 4 LED control lines that can be used as general purpose indicators or visual debugging.
  2. Qty. 4 DSP GPIOs that can be used as FPGA-> DSP interrupts or general purpose lines.

NOTES:

1. Excludes all 10 multi-gigabit transceiver differential pairs which may be optionally included upon request with alternate Altera or Xilinx FPGAs.
2. FPGA pinout supplied with sample projects.
   
   

FPGA Pinout To FMC Connector on Rev8 PCBs

Below is the connection diagram between the FPGA and the FMC connector:

FPGA Pinout To LED Control Lines

There are two set of LEDs used for debugging and system monitoring:

1. Optional set of 4 user configurable LEDs controlled by the FPGA, which may be used as general purpose indicators or visual debugging with the pinouts listed in the table below:
2. 3 LEDs controlled by the MCU which serve as status indicators for the card's initialization process during the boot phase as well as normal run. For more details, please refer to the MCU Status LEDs section of the MCU Guide.

Optional External DDR3 FPGA Memory

In addition to the DSP's main external DDR3 memory port, the FPGA has an option for its own dedicated external 32 bit DDR3 port clocked at the full 400Mhz (effective 800Mhz data rate), with a capacity totaling 256MB (64Mega x 32 bits), and expandable to 1GB (256Mega x 32 bits).

FPGA Pinout To External DDR3

Below is the table outlining the FPGA pinout to its optional external 32 bit DDR3 memory: