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SI-C667xDSP FPGA Hardware Guide



FPGA Overview

The Optional Intel-Altera Cyclone V GX device is offered in a variety of densities in the 672 pin BGA package, and is connected to the DSP via the primary 3.125Gbps-5Gbps SRIO SerDes port as well as the DSP's secondary 166.67Mhz EMIF 16 bit parallel port. The base part numbers for the Cyclone V GX devices starting with the lowest to highest densities are as follows:

5CGXFC3
5CGXFC4
5CGXFC5
5CGXFC7
5CGXFC9

Please refer to the specific Cyclone V GX FPGA datasheet for details on the architecture of the device placed on the SI-C667xDSP-PCIe board.
General information:
https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html
Datasheets:
https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-v/support.html

FPGA Mapping

Cyclone V GX FPGA Pin Mapping and Properties
Port ClassFMC BusExternal DDR3DSP->FPGA Links
FMC LA BusFMC HA BusFMC HB BusDDR3 (Internal IP)SRIO (SerDes Link Between DSP-FPGA)EMIF16 (16 bit Parallel Port Between DSP-FPGA)GPIOs & Miscellaneous Support
Signal Termination & SpeedDiff IOs: 34 @ 230Mbps (Bus Mode LVDS)Diff IOs: 24 @ 230Mbps (Bus Mode LVDS)Diff IOs: 22 @ 230Mbps (Bus Mode LVDS)256MB (64Mega x 32 bits) to 1GB (256Mega x 32 bits) @ 800Mhzx4 Lanes (8 Diff Pairs) @ 3.125GbpsEMIF16 (64k x 16 bits) @ 166.67MhzDSP_GPIO[13, 8:6], LED[7:4]
Single IOs: 68Single IOs: 48Single IOs: 44
FPGA Bank5A, 7A, 8A6A3B, 4AQL[1:0] (SerDes Ports)3A (ED[15:0]), 5B (EA[15:0] & EMIF Control)5A (LED[7:6]), 5B (GPIO[13, 8:6]), 6A (LED[5:4])
Bank VoltagesVIO_A_C2M: 1.2V-3.3V @ 5AVIO_B_M2C: 1.2V-3.3V @ 1A, or VIO_B_C2M: 3.3V (If VIO_B absent from Mezzanine)VIO_DDR3: 1.5V1.1V1.8V5A: VIO_A_C2M (LED[7:6] shared with FMC's HA & LA bus), 5B: 1.8V (GPIO[13, 8:6] shared with DSP's EMIF bus), 6A: VIO_B_M2C (LED[5:4] shared with FMC's HB bus)
VREF_A_C2M: 0.6V-3.3V (If VREF_A absent from Mezzanine), or VREF_A_M2C: 0.6V-3.3VVREF_B_M2C: 0.6V-3.3V, or VREF_B_C2M: 3.3V (If VREF_B absent from Mezzanine)VREF_DDR3: 0.75V


NOTES:

  1. VIO_A and VREF_A refers to the IO bank voltages and corresponding references for the FMC's LA and HA busses, denoted as VADJ_C2M and VREF_A_M2C respectively in the FMC Standard documentation. Similarlarly, VIO_B and VREF_B refers to the IO bank voltages and corresponding references for the FMC's HB bus.
  2. The directionality designation of C2M refers to "Carrier to Mezzanine", while M2C refers to "Mezzanine to Carrier."
  3. Bank Voltages for the VIO and VREF rails are jumper selectable, and are defaulted at 2.5V or 3.3V.
  4. FMC support signals are routed to Cyclone 5GX FPGA bank 5B with the DSP's EMIF16; FMC's M2C clock pairs [1:0] are routed to FPGA bank 7A in conjunction with the FMC's LA & HA busses, and the FMC's bidirectional clock pairs [3:2] are routed to FPGA banks 6A and 8A respectively.
  5. Differential IO pairs are compatible with Bus mode LVDS (check datasheet for FPGA pin directions for serial transceiver mode), HSTL, and Differential SSTL signaling standards.
  6. The differential signal bandwidth is limited to 230Mbps in order to support bidirectionality in bus LVDS mode. However, differential signaling speed may be dramatically increased by rerouting the circuit board so that the differential signals on the Cyclone V GX FPGA are unidirectional and known in advance to support serial LVDS transceiver mode, or alternately by upgrading to a much higher grade device (and more expensive) from Altera or Xilinx.

DSP To FPGA Interface

FPGA: Programming and Configuration

One of the main criteria for selecting the Intel-Altera Cyclone V GX series of FPGAs is the availability of the free Lite Edition of the Quartus Prime software development tool, which may be downloaded from Intel's website:
https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/download.html

After project creation and synthesis with the Quartus Prime software, the resulting configuration file (Raw Binary File with extension ".rbf") is loaded into the FPGA by an SI supplied utility run on the DSP. The FPGA is designed to boot in the Passive Serial Mode making it dependent on a processor to quickly load the configuration file, thereby removing the necessity for an onboard configuration EEPROM. The ability to load configuration files via a software utility offers an easy upgrade path by avoiding a reburn of an onboard EEPROM and being forced to reinitiate the configuration process or reboot the system.

DSP To FPGA Physical Links

SRIO Link & Pinout

The x4 lane 3.125Gbps-5Gbps SRIO SerDes port is used as a link between the DSP and the Optional expansion FPGA.

Below is the table outlining the DSP's SRIO port to the FPGA's pinout:

DSP SRIO Port to FPGA Pinout
DSP LineFPGA Bank & Pin
CLK_SRIO_PQL0-V6
CLK_SRIO_NQLO-W6
D->F0_PQL0-AD2
D->F0_NQL0-AD1
F->D0_PQL0-AE4
F->D0_NQL0-AE3
D->F1_PQL0-AB2
D->F1_NQL0-AB1
F->D1_PQL0-AC4
F->D1_NQL0-AC3
D->F2_PQL0-Y2
D->F2_NQL0-Y1
F->D2_PQL0-AA4
F->D2_NQL0-AA3
D->F3_PQL1-V2
D->F3_NQL1-V1
F->D3_PQL1-W4
F->D3_NQL1-W3


EMIF Bus & Pinout

The 16 bit 166.67Mhz EMIF16 parallel port is used as a secondary link between the DSP and the Optional expansion FPGA (which serves as a bridge to the FMC interface), with an externally accessible range of 64k x 16 bits, mapped on the DSP's CE0 (maybe set instead to CE1 upon request).

Below is the table outlining the DSP's EMIF port to the FPGA's pinout:

DSP EMIF Bus to FPGA Pinout
DSP EDataFPGA Bank & PinDSP EAddress & ControlFPGA Bank & Pin
ED153A-U7EA155B-V23
ED143A-T7EA145B-P22
ED133A-Y8EA135B-W26
ED123A-AA7EA125B-U26
ED113A-AD7EA115B-T24
ED103A-AB6EA105B-V24
ED93A-W8EA95B-T26
ED83A-AD6EA85B-P21
ED73A-AA6EA75B-W25
ED63A-V8EA65B-U25
ED53A-R8EA55B-T23
ED43A-Y9EA45B-U24
ED33A-R10EA35B-AB26
ED23A-R9EA25B-R24
ED13A-T8EA15B-V25
ED03A-P8EA05B-R25
--EWEn5B-R23
--EWAIT05B-P23
--EEOEn5B-R26
--ECE0n5B-N25
--ERWn5B-P26


GPIOs & Pinout

Four DSP GPIOs may be used as FPGA-> DSP interrupts or as user defined general purpose lines.

Below is the table outlining the FPGA's pinout to the DSP's GPIO port:

DSP GPIOs to FPGA Pinout
DSP LineFPGA Bank & Pin
GPIO135B-AB25
GPIO85B-AC25
GPIO75B-AD25
GPIO65B-P20



FMC Interface & Expansion

The expansion site incorporates the widely adopted FMC standard, which allows for the integration of either the SI-MOD32xx-FMC module, a wide variety of most third party LPC modules (and some HPC modules, please consult SI in order to evaluate compatibility), or a custom module design where SI will provide all of the necessary support for successful project completion.

The FPGA serves as a bridge between the DSP and the FMC expansion site with these general properties and user defined I/O signals:

  • Single Width FMC site (HPC 400 pin connector).
  • Bank Voltages for the VIO and VREF rails are jumper selectable.
  • User defined IOs, for a total of 80 differential pairs or 160 single ended IOs:
    1. Complete LA bus: 34 differential IO pairs or 68 single ended IOs (compatible with LPC modules).
    2. Complete HA bus: 24 differential IO pairs or 48 single ended IOs (compatible with HPC modules).
    3. Complete HB bus: 22 differential IO pairs or 44 single ended IOs (compatible with HPC modules).
  • Clock pairs:
    1. Qty. 2 differential clock pairs [1:0] from Mezzanine to Carrier.
    2. Qty. 2 differential bidirectional clock pairs [3:2].
  • FMC support signals for power monitoring and presence of FMC module.
  • Miscellaneous support lines:
    1. Qty. 4 LED control lines that can be used as general purpose indicators or visual debugging.
    2. Qty. 4 DSP GPIOs that can be used as FPGA-> DSP interrupts or general purpose lines.

NOTES:

  1. Excludes all 10 multi-gigabit transceiver differential pairs which may be optionally included upon request with alternate Altera or Xilinx FPGAs.
  2. FPGA pinout supplied with sample projects.

FPGA Pinout To FMC Connector on Rev8 PCBs

Below is the connection diagram between the FPGA and the FMC connector:

FPGA Pinout to FMC HPC Connector
 Extra FMC HPC ColumnsFMC LPC ColumnsExtra FMC HPC ColumnsFMC LPC ColumnsExtra FMC HPC Columns
Row/Column PinKJHGFEDCBA
1VREF_B_M2CGNDVREF_A_M2CGNDPG_M2CGNDPG_C2MGNDFMC_CLKDIR_M2CGND
Bank 5B-Y26Bank 5B-Y25Bank 5B-AA24
2GNDCLK_FMC_BiDIR3_PPRSNT_M2C_LCLK_FMC_M2C1_PGNDHA01PGND-GND-
Bank 6A-F26Bank 5B-AA26Bank 7A-G15Bank 8A-L7
3GNDCLK_FMC_BiDIR3_NGNDCLK_FMC_M2C1_NGNDHA01NGND-GND-
Bank 6A-G26Bank 7A-G14Bank 8A-K6
4CLK_FMC_BiDIR2_PGNDCLK_FMC_M2C0_PGNDHA00PGND-GND-GND
Bank 8A-N9Bank 7A-H12Bank 5A-AC24
5CLK_FMC_BiDIR2_NGNDCLK_FMC_M2C0_NGNDHA00NGND-GND-GND
Bank 8A-M10Bank 7A-G11Bank 5A-AB24
6GNDHA03PGNDLA00PGNDHA05PGND-GND-
Bank 5A-T19Bank 8A-H7Bank 5A-W20
7HA02PHA03NLA02PLA00NHA04PHA05NGND-GND-
Bank 5A-A22Bank 5A-U20Bank 8A-K8Bank 8A-J7Bank 7A-M11Bank 5A-W21
8HA02NGNDLA02NGNDHA04NGNDLA01PGND-GND
Bank 5A-A23Bank 8A-J8Bank 7A-L11Bank 8A-K10
9GNDHA07PGNDLA03PGNDHA09PLA01NGND-GND
Bank 5A-Y23Bank 7A-J12Bank 7A-C20Bank 8A-J10
10HA06PHA07NLA04PLA03NHA08PHA09NGNDLA06PGND-
Bank 7A-L12Bank 5A-Y24Bank 5A-V22Bank 7A-J11Bank 7A-C23Bank 7A-B19Bank 7A-N12
11HA06NGNDLA04NGNDHA08NGNDLA05PLA06NGND-
Bank 7A-K11Bank 5A-U22Bank 7A-C22Bank 7A-E18Bank 7A-M12
12GNDHA11PGNDLA08PGNDHA13PLA05NGND-GND
Bank 8A-M9Bank 7A-E20Bank 8A-F6Bank 7A-F18
13HA10PHA11NLA07PLA08NHA12PHA13NGNDGND-GND
Bank 7A-G12Bank 8A-L9Bank 7A-E16Bank 7A-E19Bank 7A-D18Bank 8A-G6
14HA10NGNDLA07NGNDHA12NGNDLA09PLA10PGND-
Bank 7A-F12Bank 7A-D16Bank 7A-D17Bank 7A-D21Bank 7A-B24
15GNDHA14PGNDLA12PGNDHA16PLA09NLA10NGND-
Bank 7A-C19Bank 7A-H14Bank 7A-C17Bank 7A-D20Bank 7A-A24
16HA17PHA14NLA11PLA12NHA15PHA16NGNDGND-GND
Bank 7A-H15Bank 7A-C18Bank 7A-B15Bank 7A-H13Bank 7A-F16Bank 7A-B17
17HA17NGNDLA11NGNDHA15NGNDLA13PGND-GND
Bank 7A-J16Bank 7A-C15Bank 7A-E15Bank 7A-E10
18GNDHA18PGNDLA16PGNDHA20PLA13NLA14PGND-
Bank 8A-H8Bank 7A-H18Bank 8A-H10Bank 7A-E11Bank 7A-A23
19HA21PHA18NLA15PLA16NHA19PHA20NGNDLA14NGND-
Bank 7A-G16Bank 8A-H9Bank 8A-D8Bank 7A-H17Bank 8A-G7Bank 8A-L10Bank 7A-A22
20HA21NGNDLA15NGNDHA19NGNDLA17PGND-GND
Bank 7A-G17Bank 8A-E9Bank 8A-F7Bank 7A-B22
21GNDHA22PGNDLA20PGNDHB03PLA17NGND-GND
Bank 7A-C14Bank 8A-D6Bank 6A-N24Bank 7A-A21
22HA23PHA22NLA19PLA20NHB02PHB03NGNDLA18PGND-
Bank 7A-E13Bank 7A-D15Bank 7A-A14Bank 8A-E6Bank 6A-M25Bank 6A-M24Bank 7A-B21
23HA23NGNDLA19NGNDHB02NGNDLA23PLA18NGND-
Bank 7A-D13Bank 7A-B14Bank 6A-M26Bank 7A-A19Bank 7A-B20
24GNDHB01PGNDLA22PGNDHB05PLA23NGND-GND
Bank 6A-N23Bank 7A-B12Bank 6A-L23Bank 7A-A18
25HB00PHB01NLA21PLA22NHB04PHB05NGNDGND-GND
Bank 6A-J20Bank 6A-M22Bank 7A-A8Bank 7A-A13Bank 6A-L22Bank 6A-L24
26HB00NGNDLA21NGNDHB04NGNDLA26PLA27PGND-
Bank 6A-J21Bank 7A-A9Bank 6A-K21Bank 7A-A12Bank 7A-A17
27GNDHB07PGNDLA25PGNDHB09PLA26NLA27NGND-
Bank 6A-K25Bank 7A-C13Bank 6A-J25Bank 7A-B11Bank 7A-A16
28HB06PHB07NLA24PLA25NHB08PHB09NGNDGND-GND
Bank 6A-K24Bank 6A-K26Bank 7A-D11Bank 7A-C12Bank 6A-H23Bank 6A-J26
29HB06NGNDLA24NGNDHB08NGNDTCKGND-GND
Bank 6A-K23Bank 7A-D12Bank 6A-H24
30GNDHB11PGNDLA29PGNDHB13PTDISCLGND-
Bank 6A-H22Bank 7A-C9Bank 6A-G25
31HB10PHB11NLA28PLA29NHB12PHB13NTDOSDAGND-
Bank 6A-E21Bank 6A-J23Bank 8A-D7Bank 7A-B9Bank 6A-F23Bank 6A-H25
32HB10NGNDLA28NGNDHB12NGND3.3V AUXGND-GND
Bank 6A-F22Bank 8A-C7Bank 6A-G22
33GNDHB15PGNDLA31PGNDHB19PTMSGND-GND
Bank 6A-F24Bank 7A-B10Bank 6A-D26
34HB14PHB15NLA30PLA31NHB16PHB19NTRST_LGA0 (msb)GND-
Bank 6A-D22Bank 6A-G24Bank 7A-D10Bank 7A-A11Bank 6A-B25Bank 6A-E26
35HB14NGNDLA30NGNDHB16NGNDGA1 (lsb)12VGND-
Bank 6A-E23Bank 7A-C10Bank 6A-B26
36GNDHB18PGNDLA33PGNDHB21P3.3VGND-GND
Bank 6A-G20Bank 8A-A5Bank 6A-D25
37HB17PHB18NLA32PLA33NHB20PHB21NGND12V-GND
Bank 6A-H19Bank 6A-F21Bank 8A-A7Bank 8A-B6Bank 6A-E24Bank 6A-C25
38HB17NGNDLA32NGNDHB20NGND3.3VGNDGND-
Bank 6A-H20Bank 8A-B7Bank 6A-E25
39GNDVIO_B_M2CGNDVADJ_C2MGNDVADJ_C2MGND3.3VGND-
40VIO_B_M2CGNDVADJ_C2MGNDVADJ_C2MGND3.3VGND-GND


FPGA Pinout To LED Control Lines

There are two set of LEDs used for debugging and system monitoring:

  1. Optional set of 4 user configurable LEDs controlled by the FPGA, which may be used as general purpose indicators or visual debugging with the pinouts listed in the table below:
  2. 3 LEDs controlled by the MCU which serve as status indicators for the card's initialization process during the boot phase as well as normal run. For more details, please refer to the MCU Status LEDs section of the MCU Guide.
FPGA Pinout to LED Control Lines
LEDFPGA Bank & Pin
LED75A-AC23
LED65A-AC22
LED56A-M21
LED46A-N20



Optional External DDR3 FPGA Memory

In addition to the DSP's main external DDR3 memory port, the FPGA has an option for its own dedicated external 32 bit DDR3 port clocked at the full 400Mhz (effective 800Mhz data rate), with a capacity totaling 256MB (64Mega x 32 bits), and expandable to 1GB (256Mega x 32 bits).

FPGA Pinout To External DDR3

Below is the table outlining the FPGA pinout to its optional external 32 bit DDR3 memory:

FPGA Pinout To External DDR3
External DDR3 DataFPGA Bank & PinExternal DDR3 Address & ControlFPGA Bank & Pin
DQS3P4A-W16--
DQS3N4A-W17--
DM34A-AE24--
DQ314A-AF23--
DQ304A-AF16--
DQ294A-AF17--
DQ284A-AD23--
DQ274A-AD21--
DQ264A-AE15--
DQ254A-AE16--
DQ244A-AC20--
DQS2P4A-V15--
DQS2N4A-W15--
DM24A-AE20--
DQ234A-AE21--
DQ224A-AC17--
DQ214A-AB17--
DQ204A-AF21--
DQ194A-AF19--
DQ184A-AD16--
DQ174A-AD17--
DQ164A-AC18--
DQS1P4A-U14--
DQS1N4A-V14--
DM14A-AE18--
DQ154A-AF18A153B-Y11
DQ144A-AB16A143B-W11
DQ134A-AA16A133B-AC10
DQ124A-AE14A123B-AB10
DQ114A-AF13A113B-AC8
DQ104A-AC15A103B-AC9
DQ94A-AB15A93B-AB11
DQ84A-AC14A83B-AB12
DQS0P4A-V13--
DQS0N4A-W13--
DM04A-AF11--
DQ74A-AF12A73B-AF9
DQ64A-Y13A63B-AE9
DQ54A-W12A53B-U11
DQ44A-AD10A43B-U10
DQ34A-AD12A33B-AF8
DQ24A-AA14A23B-AF7
DQ14A-Y14A13B-AF6
DQ04A-AD11A03B-AE6
--BA23B-AE8
--BA13B-AD8
--BA03B-V10
--CLK0P3B-N10
--CLK0N3B-P10
--CLKEN04A-AF14
--RESET4A-AF19
--CEn03B-R11
--WEn3B-T9
--CASn3B-W10
--RASn3B-Y10
--ODT04A-AD13