Tiva uC Guide

Tiva MCU - TM4C123FH6PM

From TI's Tiva family, the TM4C123FH6PM is an ARM Cortex-M4F class of microcontroller (MCU) is used to control and monitor the peripheral circuitry, as well as booting the DSP itself. The MCU has 256k of internal NVRAM (flash) used to store constants and tables for both the peripheral circuitry as well as the DSP's boot mode value, which may be altered by the SI sample utility.

Four (4) of the MCU's serial ports are used as follows:

USB: a dedicated OTG uUSB port used to communicate with a host PC using the SI sample utility; the uUSB port is NOT connected to the DSP and is only intended for board configuration.
I2C0: configured as a slave mapped at the DSP's I2C master address 0x50, used to communicate directly with the DSP.
I2C3: configured as a master and only connected to communicate with the PM bus of the external main power device that supplies the 1VAR rail to the DSP, mapped at address 0x22.
SPI2: configured as a master and only connected to set up the CDCM6208 external clock generator that feeds the DSP's clock inputs.

Upon power up, the MCU launches all of the peripheral circuitry including power and clocking, and once successful it will proceed to activate the DSP. This activation includes deasserting the DSP's RESET line in order to boot the DSP, at which point the DSP will retrieve all of the essential boot information from the MCU's internal NVRAM. The overall boot time of the DSP card is within 50msec~75msec.

Please refer to TI's Tiva documentation for more details:
https://www.ti.com/product/TM4C123FH6PM

MCU Flash

Flash 0x0000_0000 - 0x0004_0000 = 256KB
Flash Block size = 0x400 bytes

Memory Map

Tiva Memory Map
Script	Memory Type	Usage	Starting~Ending Address	Length	Used/Not Used (% Used)	Attributes	Notes
CMD	SRAM	SRAM	0x2000_0000~0x2000_7FFF	0x8000 (32KB)	0x2AF9/0x5507 (33.6%)	RWX	Application uses internal RAM for data.
	NVRAM	APP_FLASH	0x0_0000~0x2_FFFF	0x3_0000 (192KB)	0x62A0/0x0002_9D60 (12.8%)	R-X	Application resides and executes from internal flash.
		I2C E2PROM TABLE (PCIe)	0x3_0000~0x3_01FF	0x0200 (512B)	0x0052/0x01AE (4%)	RWX	MCU's I2C0 slave is linked to the DSP's I2C master and is accessed after reset with boot parameters, mapped at 0x50. The table contains values for an I2C Extended Boot cycle to ultimately boot as a PCIe Endpoint device.
		I2C E2PROM TABLE (SPI)	0x3_0200~0x3_03FF	0x0200 (512B)	0x0052/0x01AE (4%)		MCU's I2C0 slave is linked to the DSP's I2C master and is accessed after reset with boot parameters, mapped at 0x50. The table contains values for an I2C Extended Boot cycle to ultimately boot from the external SPI flash device.
		I2C EBM	0x3_0400~0x3_07FF	0x0400 (1KB)	0x0004/0x003FC (1%)		Single DWord value that sets the I2C Extended or Secondary Boot Mode.
		n/u	0x3_0800~0x3_0FFF	0x0800 (2KB)	0x0000/0x0800 (0%)		Not used.
		BOOT MODE	0x3_1000~0x3_13FF	0x0004 (4B)	0x0004/0x0400 (1%)		Single DWord value that sets the DSP's hardware boot mode along the DSP's GPIO lines, effectively substituting for a DIP switch.
		REVISION ID	0x3_1400~0x3_17FF	0x0004 (4B)	0x0004/0x0400 (1%)		Format: ID:Counter:MM:DD:YY (defaulted to 0x0002_1115).
		PM STATUS FLAG	0x3_1800~0x3_1BFF	0x0004 (4B)	0x0004/0x0400 (1%)		Single DWord value that reflects the status of the power module for the 1V variable DSP supply rail.
		CLOCK	0x3_1C00~0x3_1FFF	0x0400 (1KB)	0x00xx/0x0400 (x%)		MCU's SPI2 is linked to the CDCM6208 external clock generator and loads its parameters.
		POWER	0x3_2000~0x3_27FF	0x0800 (2KB)	0x059B/0x0265 (70%)		MCU's I2C3 master is linked to the power module for the 1V variable DSP supply rail, mapped at 0x22.
		n/u	0x3_2800~0x3_2BFF	0x0400 (1KB)	0x0000/0x0400 (0%)		Not used.
NON-CMD		LOG_ADDR	0x3_2C00~0x3_2FFF	0x0400 (1KB)	0xXXXX/0x0400 (x%)	R--	Used for log info.
		DEBUG_ADDR	0x3_3000~0x3_3FFF	0x1000 (4KB)	0xYYYY/0x1000 (Y%)		Used for output errors per run.
		n/u	0x3_40000~x3_FFFF	0xC000 (48KB)	0x0000/0xC000 (0%)		Not used.

NOTES:

Gaps of the NVRAM mapping have been left open for future use and currently unused.
R: Read, W: Write, X: Execute.

MCU Status LEDs

There are two set of LEDs used for debugging and system monitoring:

3 LEDs controlled by the MCU which serve as status indicators for the card's initialization process during the boot phase as well as normal run.
Optional set of 4 user configurable LEDs controlled by the FPGA. For more details, please refer to the FPGA Pinout To LED Control Lines section of the FPGA Hardware Guide.

MCU Controlled Status LEDs
Hex Value	LED Pattern	Peripheral In Sequence	Status
0x0	Off-Off-Off	None	Normal Operation
0x1	Off-Off-Green	DVDD18	1st DSP Power Rail (1.8Vdc)
0x2	Off-Yellow-Off	CVDD VAR	2nd DSP Power Rail (1Vdc Variable)
0x3	Off-Yellow-Green	CVDD1	3rd DSP Power Rail (1Vdc)
0x4	Red-Off-Off	DVDD15	4th DSP Power Rail (1.5Vdc)
0x5	Red-Off-Green	FVDD11	1st FPGA Power Rail (1.1Vdc)
0x6	Red-Yellow-Off	External PLL & DSP_Reset-Statn	DSP Activation (External PLL & DSP Reset/Status)
0x7	Red-Yellow-Green	FVDDR15	2nd FPGA Power Rail (1.5Vdc)

NOTES:

An earlier version of MCU firmware only enables a single green LED to indicate that the DSP card initiated properly with all power rails and external clocking in working order.