SI IPC

How IPC Works

Summary: A description of the Sheldon Instruments IPC implementation
Status: Stable
Version: 2014-09-14
Prerequisites: TI's IPC package: ipc_3_23_00_01

Inter-Processor Communication (also known to us as messaging), provides a method for exchanging information between processors. Where as the TI implementation requires the use of SYSBios, the simplified SI version does not.

Models

Notification - interrupt driven messages and events
Queue - message queues between processors

Notifcation

The notification model uses interrupts to notify a processor of an incoming message. Cores are protected using hardware semaphores and any core may send a message to any other core in addition to a message. These messages may also be tied to events such that a message received will also trigger a function on the receiver core.

Queue

The Message Queue model uses a message Queue to store a FIFO list of messages onto each core. Any core can send and receive messages from any other core. These messages are stored inside a local FIFO.

Performance

The SI implementation of the IPC models is much simpler than the TI versions. The SI versions lack some of the more nuanced features offered by the TI library in order to achieve a simpler, faster, and smaller profile.

The following shows a cycle count comparison between Message Queue implementations:

Texas Instruments Library		Sheldon Instruments Library
Send	Receive	Send	Receive
0x1A87	0x25AB	0x2E9	0x1FA
0x1a85	0x254F	0x2E9	0x1FA
0x10DE	0x2418	0x2E9	0x1FA
0x1221	0x2575	0x2E9	0x1FA
0x10df	0x2408	0x2E9	0x1FA

These numbers represent changes in the Time Stamp Counter measured on the respective cores
These numbers only represent a comparison of similar actions and not an accurate reflection of actual times needed to complete operations as they rely on commands to coordinate cores. This is only intended to give a rough idea of time differences.
The SI implementation uses the same underlying hardware but loses features such as priority and dynamic allocation.
As can be seen, the SI models are more deterministic as well. This also depends on your project usage of the cores.

Notes

The SI implementation is designed to resemble the TI library in many ways while removing much of the complexity. Some configurability is maintained but finer details have been stripped in order to keep the interface faster, smaller, and simpler to use.

User's Guide

Guide for more detailed information on using SI's IPC models.