Summary: A description of the Sheldon Instruments IPC implementation Status: Stable Version: 2014-09-14 Prerequisites: TI's IPC package: ipc_3_23_00_01 Maintainer: [[~Timothy Whipple] Categories: DSP, IPC, Messages
Inter-Processor Communication, also known to us as messaging, provides a method for exchanging information between processors. Where as the TI implementation requires the use of SYSBios, our simplified version does not.
The notification model using interrupts to notify a processor of an incoming message. Cores are protected using hardware semaphores and any core may send a message to any other core in addition to a message. These messages may also be tied to events such that a message received will also trigger a function on the receiver core.
The Message Queue model uses a message Queue to store a FIFO list of messages on each core. Any core can send and receive messages from any other core. These messages are stored in a local FIFO.
The SI implementation of the IPC models is much simpler than the TI versions. These versions lack some of the more nuanced features offered by the TI library in order to achieve a simpler, faster, and smaller profile.
The following shows a cycle count comparison between Message Queue implementations:
Texas Instruments Library | Sheldon Instruments Library | ||
Send | Receive | Send | Receive |
0x1A87 | 0x25AB | 0x2E9 | 0x1FA |
0x1a85 | 0x254F | 0x2E9 | 0x1FA |
0x10DE | 0x2418 | 0x2E9 | 0x1FA |
0x1221 | 0x2575 | 0x2E9 | 0x1FA |
0x10df | 0x2408 | 0x2E9 | 0x1FA |
The SI implementation is designed to resemble the TI library in many ways but removes much of the complexity. Some configurabilty is maintained but finer details have been stripped to keep the interface faster, smaller, and simpler to use.
A description of the Sheldon Instruments IPC implementation