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IPC Guidelines


Summary: A description of the Sheldon Instruments IPC implementation Status: Stable Version: 2014-09-14 Prerequisites: TI's IPC package: ipc_3_23_00_01 Maintainer: [[~Timothy Whipple] Categories: DSP, IPC, Messages

How IPC Works

Inter-Processor Communication, also known to us as messaging, 
provides a method for exchanging information between processors. 
Where as the TI implementation requires the use of SYSBios, 
our simplified version does not. 

Models

  1. Notification - interrupt driven messages and events
  2. Queue - message queues between processors

Notifcation

The notification model using interrupts to notify a processor of an incoming message. Cores are protected using hardware semaphores and any core may send a message to any other core in addition to a message. These messages may also be tied to events such that a message received will also trigger a function on the receiver core.

Queue

The Message Queue model uses a message Queue to store a FIFO list of messages on each core. Any core can send and receive messages from any other core. These messages are stored in a local FIFO.

Performance

The SI implementation of the IPC models is much simpler than the TI versions. These versions lack some of the more nuanced features offered by the TI library in order to achieve a simpler, faster, and smaller profile.

The following shows a cycle count comparison between Message Queue implementations:

Texas Instruments LibrarySheldon Instruments Library
SendReceiveSendReceive
0x1A870x25AB0x2E90x1FA
0x1a850x254F0x2E90x1FA
0x10DE0x24180x2E90x1FA
0x12210x25750x2E90x1FA
0x10df0x24080x2E90x1FA
  • These numbers represent changes in the Time Stamp Counter measured on the respective cores
  • These numbers only represent a comparison of similar actions and not an accurate reflection of actual times needed to complete operations as they rely on commands to coordinate cores. This is only intended to give a rough idea of time differences.
  • The SI implementation uses the same underlying hardware but loses features such as priority and dynamic allocation.
  • As you can see the SI models are more deterministic as well. This also depends on your project usage of the cores.

Notes

The SI implementation is designed to resemble the TI library in many ways but removes much of the complexity. Some configurabilty is maintained but finer details have been stripped to keep the interface faster, smaller, and simpler to use.

User's Guide

  • Guide for more detailed information on using SI's IPC models.

See also

  • Interrupts for more information about interrupts
  • Messages for more information about messages
  • Example for an example project

A description of the Sheldon Instruments IPC implementation