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SI-MOD32xx Register Mapping

Below is a complete summary of registers:

SI-MOD32xx Register Mapping
Section	Registers	Base Address: 32bit Boundary (Hex)	Depth x Width (Bits)	Direction	Initial Value
ADC Section	ADC_FIFO	Base+0x0000~0x01FF	64 x 64	R	0x0
	ADC[0:3]_CSR0	Base+0x0010~0x001C	1 x 16	R/W
	ADC[0:3]_CFG	Base+0x0020~0x002C		W
	ADC[0:3]_SAMPLE_CNT	Base+0x0030~0x003C		W
DAC Section	DAC0_DATA	Base+0x8000		R/W
	DAC0_CMD_ADDR	Base+0x8004
	DAC0_CSR[0:1]	Base+0x8008~0x800C
	DAC0_PLAY_MEMSIZE	Base+0x8010
	DAC0_TOGGLE_CNT	Base+0x8014
	DAC0_MEM	Base+0xC000~0xCFFF	1k x 16
	DAC1_DATA	Base+0xA000	1 x 16
	DAC1_CMD_ADDR	Base+0xA004
	DAC1_CSR[0:1]	Base+0xA008~0xA00C
	DAC1_PLAY_MEMSIZE	Base+0xA010
	DAC1_TOGGLE_CNT	Base+0xA014
	DAC1_MEM	Base+0x1_0000~0x1_0FFF	1k x 16
DIO Section	DIO_DATA_LW	Base+0x0200	1 x 16	R/W
	DIO_DATA_HW	Base+0x0204		R/W
	DIO_CSR0	Base+0x0208		R/W

NOTES:

1. Carrier Processor Mapping:
   1. Keystone I DSP EMIF Base Address = 0x7000_0000.
   2. Keystone I DSP SRIO Base Address = TBD.
   3. Sitara PRU Base Address = TBD.

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ADC Section

The FPGA controls up to four (4) ADAS3022, 16 bit, 8 channel 1Mhz additive sampling ADC devices, for up to a maximum of 32 input channels.

ADC Register Mapping

ADC_FIFO
The ADC_FIFO is configured as a 64x64 FIFO memory and serves as an access point to all four (4) ADCs. Each FIFO location is 1x64 bits, and concatenates the simultaneously available single input channel from each of the four corresponding ADCs. The FIFO pointer is automatically incremented after each successive FIFO access in a round-robin process.

For example:
1st read -> ADC3_1st Channel + ADC2_1st Channel + ADC1_1st Channel + ADC0_1st Channel
2nd read -> ADC3_2nd Channel + ADC2_2nd Channel + ADC1_2nd Channel + ADC0_2nd Channel
3rd read -> ADC3_3rd Channel + ADC2_3rd Channel + ADC1_3rd Channel + ADC0_3rd Channel
4th read -> ADC3_4th Channel + ADC2_4th Channel + ADC1_4th Channel + ADC0_4th Channel
...
...
nth read -> ADC3_nth Channel + ADC2_nth Channel + ADC1_nth Channel + ADC0_nth Channel
...
...
and so forth.

Register Name		Description	Address (HEX)
ADC_FIFO		64 x 64 ADC FIFO Memory	Base+0x0000
Bit Position	Name	Description	Direction	Initial Value
63:48	ADC3_CHANNELn[15:0], n=0~7	64 x 64 ADC FIFO Memory Block	R	0
47:32	ADC2_CHANNELn[15:0], n=0~7
31:16	ADC1_CHANNELn[15:0], n=0~7
15:0	ADC0_CHANNELn[15:0], n=0~7

ADC_CSR0
ADC_CSR0 is a control and status register for configuring and controlling the FPGA's interface to the ADCs along with the internal FPGA FIFO.

Register Name		Description	Address (HEX)
ADC_CSR0		ADC Control & Status Register	Base+0x0010
Bit Position	Name	Description	Direction	Initial Value
15:10	-	-	-	0
9	ADC_FIFO_FULL_STAT	ADC FIFO Full Status	R	0
		0 = ADC FIFO NOT Full
		1 = ADC FIFO Full
8	ADC_FIFO_EMPTY_STAT	ADC FIFO Empty Status	R	0
		0 = ADC FIFO NOT Empty
		1 = ADC FIFO Empty
7:5	-	-	-	0
4	ADC_CFG_WR	Write Configuration to ADCs	W	0
3:2	-	-	-	0
1	ADC_EN	ADC Enable Data Acquisition	W	0
		0 = ADC DISabled
		1 = ADC ENabled
0	ADC_FIFO_RST	ADC & FIFO Reset	W	0

NOTE: ADC_CSR0 may be expanded such that each ADC circuit is assigned its own register, for example ADC0_CSR0 assigned to ADC0, ADC1_CSR0 assigned to ADC1, etc.

ADC_CFG
ADC_CFG is a 16 bit control register that mirrors a value to be passed on to the ADAS3022's internal 16 bit control register by the same name, and is used to configure its many operating modes including input termination along with its internal PGA.

Register Name		Description	Address (HEX)
ADC_CFG		ADAS3022 Configuration Register	Base+0x0020
Bit Position	Name	Description	Direction	Initial Value
15:0	ADC_CFG[15:0]	ADAS3022 device configuration value.	W	0

NOTE: ADC_CFG may be expanded such that each ADC circuit is assigned its own register, for example ADC0_CFG assigned to ADC0, ADC1_CFG assigned to ADC1, etc.

ADC_SAMPLECK_CNT
In order to set the ADC sample clock rate, the ADC_SAMPLECK_CNT register a 16 bit hex value used as a denominator to divide a high speed reference clock numerator; in this case the FPGA Main Clock of 200Mhz.

The ADC sample rate clock uses the following formula:
ADC Sample Rate = FPGA Clock Frequency/(ADC_SAMPLECK_CNT + 1)

For example, to set the ADC Sample Rate = 1MHz, we would use the following numbers:
FPGA Clock Frequency = 200Mhz,
ADC_SAMPLECK_CNT = 199 (0xC7)

=>ADC Sample Rate = 200Mhz/(199+1) = 1Mhz

Register Name		Description	Address (HEX)
ADC_SAMPLECK_CNT		ADC Sample Clock Denominator	Base+0x0030
Bit Position	Name	Description	Direction	Initial Value
15:0	ADC_SAMPLECK_CNT[15:0]	Denominator value to set ADC sample rate that divides 200Mhz FPGA reference numerator.	W	0

NOTE: ADC_SAMPLECK_CNT may be expanded such that each ADC circuit is assigned its own register, for example ADC0_SAMPLECK_CNT assigned to ADC0, ADC1_SAMPLECK_CNT assigned to ADC1, etc.

NOTES:

1. Carrier Processor Mapping:
   1. Keystone I DSP EMIF Base Address = 0x7000_0000.
   2. Keystone I DSP SRIO Base Address = TBD.
   3. Sitara PRU Base Address = TBD.
2. For ADC hardware details, please refer to the ADAS3022 data sheet.
   

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DAC Section

The FPGA controls up to two (2) LTC2666, 16 bit, 8 channel 250khz additive updating DAC devices, for up to a maximum of 16 output channels.

DAC Register Mapping

The LTC2666 has an SPI 24bit serial interface to the FPGA. The most significant nibble is the command, the next nibble is the address for the specific internal DAC0 output (select 0..7), and the remaining lower 16-bits are the data for the DAC output value.

DAC_DATA
The DAC_DATA register is a 16 bit value that is to be directly transferred to a DAC output channel, after the 8 bit command and address fields are written into the DAC_CMD_ADDR register. Both register contents are concatenated to form a 24 bit value that is then directly transferred to the DAC. The 16 bit data field is represented as an unsigned U16 value, with outputs defaulted to operate in the maximum bipolar range of +/-10V (20Vpp). Please consult the factory if the DAC output range may need to be configured in a different default mode as there are many combinations of unipolar and bipolar modes available.

Register Name		Description	Address (HEX)
DACn_DATA		DACn Data Register	DAC0 = Base+0x8000
			DAC1 = Base+0xA000
Bit Position	Name	Description	Direction	Initial Value
15:0	DACn_DATA[15:0]	U16 value transferred to DACn output	R/W	0

DAC_CMD_ADDR
The DAC_CMD_ADDR register fields are composed of the 4 bit command and a 4 bit address. A write to the DAC_CMD_ADDR register will initiate a transfer to the DAC using a 24 bit stream that is formed by concatenating its contents with the value already inside the DAC_DATA register.

Register Name		Description	Address (HEX)
DACn_CMD_ADDR		DACn Command Address Register	DAC0_CMD_ADDR = Base+0x8004
			DAC1_CMD_ADDR = Base+0xA004
Bit Position	Name	Description	Direction	Initial Value
15:8	-	-	R/W	0
7:4	DACn_CMD[3:0]	4 bit command field per output channel
3:0	DACn_ADDR[3:0]	4 bit address field where the 3lsbs are used to define the specific DACn output channel [7:0] to be updated.

DAC_CSR0
Bit 0 of the DAC_CSR0 register controls the external CLRn signal line to the DACs. Its default value is a '1'; toggling this bit (first writing a '0' followed by writing a '1') will clear the DACs, and is necessary in order to initialize the DACs before accessing them.

Register Name		Description	Address (HEX)
DACn_CSR0		DACn Control & Status Register 0	DAC0_CSR0 = Base+0x8008
			DAC1_CSR0 = Base+0xA008
Bit Position	Name	Description	Direction	Initial Value
15:1	-	-	R/W	0
0	DACn_CLR	Clears all DACn outputs.		1
		0 = DACn Cleared
		1 = DACn ENabled (default)

DAC_CSR1
Bit 0 of the DAC_CSR1 register will enable the DAC Memory Playback mode. Enabling the DAC Memory Playback mode will disable all direct accesses to the DAC and instead it will be updated with the values contained inside the DAC0_MEM buffer.

The DAC Memory Playback mode will transfer the contents of the DAC0_MEM buffer to the DACs whose size is defined by the 10 bit DAC0_PLAY_MEMSIZE register. The DAC Memory Playback mode will repeat this loop until disabled by writing a '0' to bit 0 of the DAC0_CSR1 register.

Register Name		Description	Address (HEX)
DACn_CSR1		DACn Control & Status Register 1	DAC0 = Base+0x800C
			DAC1 = Base+0xA00C
Bit Position	Name	Description	Direction	Initial Value
15:1	-	-	R/W	0
0	DACn_PLAYMODE_SEL	Controls the DAC Memory Playback mode.
		0 = DISable DACn Memory Playback, DACn Updated directly by accessing the DACn_DATA register (default).
		1 = ENable DACn Memory Playback mode where values are updated from the contents inside of DAC_MEM buffer.

DAC_PLAY_MEMSIZE
DAC_PLAY_MEMSIZE is a 10-bit register that is used to define the size of the FPGA's DACn Memory Playback memory buffer. When added to the DACn_MEM base address, note that this value also serves as the last address to be accessed from the DACn Memory Playback buffer.

Register Name		Description	Address (HEX)
DACn_PLAY_MEMSIZE		DACn Playback Memory Size Register	DAC0 = Base+0x8010
			DAC1 = Base+0xA010
Bit Position	Name	Description	Direction	Initial Value
15:10	-	-	R/W	0
9:0	DACn_PLAY_MEMSIZE[9:0]	DACn Memory buffer size for playback mode, 1k maximum (default = 0x3FF).

DAC_TOGGLE_CNT

Register Name		Description	Address (HEX)
DACn_TOGGLE_CNT		DACn Toggle Counter Register	DAC0 = Base+0x8014
			DAC1 = Base+0xA014
Bit Position	Name	Description	Direction	Initial Value
15:0	DACn_TOGGLE_CNT[15:0]	-	R/W	0

DAC_MEM
DAC_MEM is the DAC Memory region for the DAC Memory Playback mode. Because the FPGA's internal memory uses a 16 bit address boundary versus the DSP's 32 bit addressing, the 1k buffer inside the FPGA will appear as a 2k sized addressable region to the DSP. Therefore, from the DSP's addressing point of view, the DAC data points will be interleaved with the DAC command/address bits.

Starting from the DSP's first address, every other address from there represents the 16-bit DAC's data values according to the following formula:
(DSP Base + 0xC000) + (n * 8)

Likewise, starting from the DSP's second address, every other address from there represents the DAC's command/address fields as shown below:
(DSP Base + 0xC004) + (n * 8)

where n is the nth data and command/address pair representing the DAC's nth channel to be written to the DAC_MEM buffer, which is to be automatically transferred to DAC's nth channel.

Therefore from the DSP's viewpoint, the FPGA's DACn_MEM mapping appears as follows:
DSP Base + 0xC000 = DACn 1st channel data
DSP Base + 0xC004 = DACn 1st channel command/address field
DSP Base + 0xC008 = DACn 2nd channel data
DSP Base + 0xC00C = DACn 2nd channel command/address field
...
...
and so on.

For example, to write a single 24 bit value of 0x30FFFF to the DAC0_MEM buffer which is to be transferred to DAC0's 1st channel, perform these following steps in sequence:

1. write the DACn's 1st channel data value 0xFFFF to address (DSP Base + 0xC000)
2. write the DACn's 1st channel command/address field 0x30 to address (DSP Base + 0xC004)

These pair of values will be automatically concatenated to form the 24 bit stream that is transferred to the DACn.

Register Name		Description	Address (HEX)
DACn_MEM		DACn Data Memory Block	DAC0 = Base+0xC000
			DAC1 = Base+0xA000
Bit Position	Name	Description	Direction	Initial Value
15:0	DACn_MEM[15:0]	DACn data, command/address fields	R/W	0

NOTES:

1. Carrier Processor Mapping:
   1. Keystone I DSP EMIF Base Address = 0x7000_0000.
   2. Keystone I DSP SRIO Base Address = TBD.
   3. Sitara PRU Base Address = TBD.
2. For DAC hardware details, please refer to the LTC2666 data sheet.
   

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Digital IO Port Section

The FPGA controls four (4) 74FCT2652 8 bit transceivers, with two (2) devices making up each 16 bit bidirectional buffered port, for a maximum thirty two (32) lines, with 3.3V~5V tolerance. When a port is configured as an input, it operates as a non-registered transceiver. Meanwhile as an output, it operates as a registered transceiver.

Digital IO Port Register Mapping

DIO_DATA
A pair of 16 bit DIO_DATA registers form the interface to the external buffered DIO port.

Register Name		Description	Address (HEX)
DIO_DATA_LW		Digital I/O Port: Low Word	Base+0x0200
Bit Position	Name	Description	Direction	Initial Value
15:0	D[15:0]	LoWord: Data[15:0] Bits	R/W	0

Register Name		Description	Address (HEX)
DIO_DATA_HW		Digital I/O Port: High Word	Base+0x0204
Bit Position	Name	Description	Direction	Initial Value
15:0	D[31:16]	HiWord: Data[31:16] Bits	R/W	0

DIO_CSR0
DIO_CSR0 is a control and status register for configuring and controlling the FPGA's interface to the transceivers.

Register Name		Description	Address (HEX)
DIO_CSR0		Buffered Digital I/O Port Control/Status Register	Base+0x0208
Bit Position	Name	Description	Direction	Initial Value
15:4	-	-	-	0
3	DIO_RDn	DIO Read Control	W	0
		0 = ENable DIO Read Control, transfer FCT2652 internal register or external DIO lines -> FPGA
		1 = DISable DIO Read Control, FCT2652 to FPGA interface in HiZ.
2	DIO_WR	DIO Write Control	W	0
		0 = DISable DIO Write Control.
		1 = ENable DIO Write Control, transfer data from FPGA -> internal FCT2652 register.
1	DIO_DIR_HW	Selects the direction of the high order 16 bit word DIO[31:16] on the buffered digital I/O port available on the dedicated digital I/O connector.	R/W	0
		0 = HiWord[31:16] is an input (default), transfer external DIO lines -> FPGA.
		1 = HiWord[31:16] is an output, transfer internal FCT2652 register written by FPGA -> external DIO lines.
0	DIO_DIR_LW	Selects the direction of the low order 16 bit word DIO[15:0] on the buffered digital I/O port available on the dedicated digital I/O connector.	R/W	0
		0 = LoWord[15:0] is an input (default), transfer external DIO lines -> FPGA.
		1 = LoWord[15:0] is an output, transfer internal FCT2652 register written by FPGA -> external DIO lines.

NOTES:

1. Carrier Processor Mapping:
   1. Keystone I DSP EMIF Base Address = 0x7000_0000.
   2. Keystone I DSP SRIO Base Address = TBD.
   3. Sitara PRU Base Address = TBD.
2. For DIO Buffer details, please refer to the 74FCT2652 data sheet.
   

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